module avalon_dtube(
    input           clk,
    input           reset,
    
    input [1:0]     as_address,
    input           as_write,
    input [31:0]    as_writedata,
	
//    input           avs_read,
//    output reg [31:0]   avs_read_data,
    
    output [5:0]    data_sel,
    output [7:0]    data_seg
);


reg [11:0] write_data;

always @ (posedge clk, negedge reset)
begin
    if (!reset) begin
        write_data <= 12'd0;
    end
    else if (as_write) begin
        case (as_address)
            2'd0:   begin write_data <= as_writedata[11:0]; end
            2'd1:   begin       end
            2'd2:   begin       end
            2'd3:   begin       end
            default:    begin   end
        endcase

    end
end


//always @ (posedge clk, negedge reset)
//begin
//    if (!reset) begin
//        avs_read_data <= 32'd0;
//    end
//    else if (avs_read) begin
//        case (avs_address)
//            2'd0:   begin avs_read_data <= write_data; end
//            2'd1:   begin       end
//            2'd2:   begin       end
//            2'd3:   begin       end
//            default:    begin   end
//        endcase
//
//    end
//end

dtube_control dtube_control_inst
(
    .clk            (clk),
    .rst_n          (reset),
    
    .data_time      (write_data),
    
    .data_sel       (data_sel),
    .data_seg       (data_seg)
);


endmodule
